This invention relates generally to computer systems and more particularly to devices used to drive signals onto and receive signals from a computer bus.
As it is known in the art, computer systems generally include a device referred to as a central processor unit which is used to execute computer instructions to perform some function. The central processing unit generally referred to as a CPU communicates with other devices in the computer system via a communications network generally referred to as a computer bus or system bus. Other devices commonly coupled to the system bus include memory systems such as main memory and more persistent type of storage systems such as magnetic disk type storage systems. These devices including the CPU are generally not connected directly to the system bus but rather are coupled to the bus through a device called a bus interface.
The bus interface device for a CPU may be quite different than that for a main memory or for a magnetic disk device. Moreover, for persistent storage such as magnetic disk, an interface module called a I/O bus adapter is often used to interface the system bus to an I/O bus (input/output bus) to which are connected several disk storage devices. In general however, all of these interfaces on a particular bus use a common set of devices called bus drivers and bus receivers to send and receive logic signals with proper voltage levels and appropriate drive capacity to insure reliable transfers of data on the bus.
As it is also known, system buses generally carry information including address information, control information, and data. Busses transfer this information in a logical manner as determined by the design of the system. This logical manner is referred to as the bus protocol.
One problem that is common with system buses is that as the performance of a CPU increases that is, as the processing speed increases, it is necessary to provide a concomitant increase in bus transfer rate. That is, it is necessary to permit more address, control, and data to be transfered at faster rates on the bus so as not to obviate the advantages obtained by use of a faster CPU.
Buses can be so-called synchronous buses in which all transfers are synchronized to a common timing signal referred to as a clock signal or the buses can be asychronous buses in which hand-shaking signals are used to transfer information as quickly as possible.
Several problems are associated with improving bus performance whether the bus is synchronous or asychronous. A characteristic called cycle time gives an indication of the speed of a bus. For a synchronous bus, a cycle can be viewed as that period of time required to complete a transfer on the bus before a new transfer can begin. This minimum period determines the maximum clock rate.
In general, the minimum cycle time for a synchronous bus is related to noise in the clock generally referred to as clock skew, propagation delay from an asserting edge of the clock to the period of time that the data appears at the output of the device connected to the bus, and delay associated with driving the bus. The delay associated with driving the bus includes two components. The first one is the propagation delay through the bus driver and the second is the period of time necessary to have the bus settle. An additional source of increase in bus cycle time is related to the setup time associated with the receiver and the propagation delay associated with propagation of data through the receiver.
The first problem of setup time is related to the amount of time prior to the receiving clock or timing signal asserting edge by which data must be present and waiting before the occurance of the clocking edge. Setup time directly affects bus cycle performance because additional time is necessary to wait to assert the clocking edge of the clock signal.
The second problem of propagation delay while not having a direct influence on bus cycle time nevertheless if excessive will affect system performance. The receiver propagation delay causes the overall system to wait before received data can be used.
Conventional bus receivers included a differential amplifier circuit which is used to amplify a received voltage with respect to a receiver reference. The received amplified voltage is fed to a master-slave flip flop to latch a digital state associated with the received voltage. One problem with this approach is that the received voltage is first amplified before it is fed to the master-slave flip flop. Thus the period of time required for the signal to be amplified contributes to the setup time of the receiver. This means that the clock cycle is extended by that amount in order to have the master-slave flip flop have valid data waiting before arrival of the clocking signal.
The use of the amplifier and master-slave flip flop in this manner also increases propagation delay. This is because the received signal propagates through the master slave flip flop before it can be used by the remaining portion of the circuit interfaced to by the receiver.
It is sometimes necessary with logic resolving devices to convert from a differential output to a single ended output. Typical techniques used to accomplish this use only one of the differential outputs as an input signal into a network whereas the other signal is typically coupled to a dummy load to preserve impedance balance.
There are several drawbacks with this approach. The chief drawback is that the presence of the load occupies space in the circuit while not directly contributing to a performance advantage. An additional problem is that the characteristics of the load can vary reducing the initial impedance match to the unused differential output and thus reducing symmetry in the circuit.